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Dive into the research topics where Jacob Savir is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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BIST pretest of ICs: Risks and benefits
Nakamura, Y., Savir, J. & Fujiwara, H., 2006, Proceedings - 24th IEEE VLSI Test Symposium. p. 142-147 6 p. 1617577. (Proceedings of the IEEE VLSI Test Symposium; vol. 2006).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2 Link opens in a new tab Scopus citations -
Coefficient-based test of parametric faults in analog circuits
Guo, Z. & Savir, J., Feb 2006, In: IEEE Transactions on Instrumentation and Measurement. 55, 1, p. 150-157 8 p.Research output: Contribution to journal › Article › peer-review
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Effect of BIST pretest on IC defect level
Nakamura, Y., Savir, J. & Fujiwara, H., Oct 2006, In: IEICE Transactions on Information and Systems. E89-D, 10, p. 2626-2636 11 p.Research output: Contribution to journal › Article › peer-review
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Built-in online and offline test of airborne digital systems
Savir, J., Jun 2005, In: IEEE Transactions on Instrumentation and Measurement. 54, 3, p. 965-974 10 p.Research output: Contribution to journal › Article › peer-review
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Defect level vs. yield and fault coverage in the presence of an unreliable BIST
Nakamura, Y., Savir, J. & Fujiwara, H., Jun 2005, In: IEICE Transactions on Information and Systems. E88-D, 6, p. 1210-1216 7 p.Research output: Contribution to journal › Article › peer-review
5 Link opens in a new tab Scopus citations