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Keyphrases
Testability
78%
Delayed Test
46%
Self-testing
45%
Combinational Circuits
43%
Built-in Self-test
41%
Parametric Faults
41%
Analog Circuits
40%
Cutting Algorithm
39%
Multiple Input Signature Register
38%
Test Vector
34%
Random Access Memory
34%
Scan Design
33%
Weighted Random Pattern
32%
Shift Register
31%
Embedded Memory
31%
Fault Coverage
30%
Test Generation
27%
Delay Faults
26%
Detection Probability
25%
Testability Design
25%
Hardware Overhead
24%
Defect Levels
24%
Fault-free
23%
Aliasing
21%
Digital Systems
21%
Random Testing
21%
Test Quality
20%
On chip
20%
Combinational Logic
19%
Circuitry
19%
Linear Time Invariant
19%
Fault Diagnosis
19%
Pattern Test
18%
Fault Detection
18%
Circuit Testing
18%
Intermittent Fault
18%
Transition Testing
16%
Latch Design
16%
Transfer Function Coefficients
16%
Fan-out
16%
Single Clock
16%
Multi-port Memory
16%
Intermittent Failure
16%
Offline Testing
16%
Memory Control
16%
Linear Feedback Shift Register
15%
Control Logic
15%
Single Input
15%
Skewed-load Tests
15%
Diagnostic Resolution
13%
Computer Science
Random Pattern
100%
Probability
58%
Fault Coverage
46%
Shift Register
42%
Detection Probability
40%
Combinational Circuit
38%
Input Signature Register
37%
embedded memory
32%
Test Generation
29%
Hardware Overhead
29%
Analog Circuit
28%
Random Access Memory
26%
build-in self-test
21%
Fault Detection
20%
Random Test Pattern
19%
Fault Diagnosis
19%
Testable Design
17%
Fault Simulation
16%
Scan Chain
16%
Combinational Logic
16%
Multiport Memory
16%
Sequential Circuit
16%
Performance Impact
16%
Lower Performance
16%
Digital System
16%
Transfer Function
16%
Aliasing
16%
Surrounding Logic
10%
Initial Value
10%
Distributed Power Generation
10%
Diagnosis
10%
Experimental Result
10%
Signature Analysis
9%
Permanent Fault
8%
linear-feedback shift register
8%
Scheduling Algorithm
8%
Random Test
7%
Aliasing Probability
7%
Test Methodology
6%
Monte Carlo Simulation
6%
System Identification
6%
Special Attention
6%
Unique Property
5%
Random Selection
5%
Test Generation Program
5%
Density Functional Theory
5%
System Clock
5%
Propagation Delay
5%
Combinational Logic Network
5%
Preprocessor
5%
