Keyphrases
Testability
87%
Built-in-self-test (BiST)
52%
Delay Test
51%
Self-testing
51%
Combinational Circuits
48%
Parametric Faults
45%
Analog Circuits
44%
Cutting Algorithm
44%
Multiple Input Signature Register
42%
Test Vector
38%
Random Access Memory
38%
Scan Design
37%
Weighted Random Patterns
36%
Embedded Memory
34%
Shift Register
34%
Fault Coverage
34%
Test Case Generation
30%
Delay Faults
30%
Detection Probability
28%
Testability Design
28%
Hardware Overhead
27%
Defect Levels
27%
Fault-free
26%
Aliasing
24%
Digital Systems
24%
Random Testing
23%
On chip
22%
Combinational Logic
22%
Circuitry
22%
Linear Time Invariant
22%
Fault Diagnosis
21%
Test Quality
21%
Pattern Test
20%
Fault Detection
20%
Circuit Testing
20%
Intermittent Fault
20%
Transition Test
18%
Multi-port Memory
18%
Latch Design
18%
Intermittent Failure
18%
Single Clock
18%
Offline Testing
18%
Memory Control
18%
Transfer Function Coefficients
18%
Fan-out
18%
Control Logic
17%
Linear Feedback Shift Register
17%
Single Input
17%
Skewed-load Tests
16%
CMOS Design
15%
Engineering
Testability
70%
Built-in Self Test
59%
Combinatorial Circuits
48%
Shift Register
40%
Input Multiple
36%
Analog Circuit
36%
Random Access Memory
29%
Digital System
26%
Detection Probability
25%
Tasks
23%
Design System
21%
Conducted Experiment
21%
Test Procedure
19%
Detail Design
18%
Logic Circuit
18%
Mode Signal
18%
Test Time
18%
Linear Time Invariant
18%
Defects
18%
Address Line
18%
Transfer Function
18%
Multiport Memory
18%
Observables
18%
Hardware Overhead
13%
Functional Operation
12%
Initial Value
12%
System Clock
12%
Propagation Delay
12%
Distributed Power Generation
12%
Circuit Test
12%
Probability of Detection
12%
Line Fault
12%
Test Line
12%
Computer System
12%
Design Rule
10%
Data Path
9%
Manufacturing Process
9%
Simplifies
9%
Feedforward
9%
Sequential Circuits
7%
Fits and Tolerances
7%
Special Attention
6%
Compression Technique
6%
Test Analysis
6%
Power Supply
6%
Illustrates
6%
Pattern Recognition
6%
Combined Method
6%
Linear Time
6%
Data Line
6%
Computer Science
Random Pattern
100%
Fault Coverage
44%
embedded memory
36%
Shift Register
34%
Test Generation
32%
Analog Circuit
32%
Detection Probability
30%
Hardware Overhead
29%
Fault Detection
28%
Random Access Memory
26%
Input Signature Register
23%
Combinational Circuit
21%
Scan Chain
21%
Combinational Logic
21%
Multiport Memory
18%
Sequential Circuit
18%
Fault Diagnosis
15%
Digital System
15%
Testable Design
14%
Test Methodology
13%
Random Test Pattern
13%
Fault Simulation
12%
Surrounding Logic
12%
Performance Impact
12%
Initial Value
12%
Unique Property
12%
Lower Performance
12%
Experimental Result
12%
Aliasing
12%
Signature Analysis
11%
build-in self-test
9%
Permanent Fault
9%
linear-feedback shift register
9%
Scheduling Algorithm
9%
Aliasing Probability
8%
Pay Special Attention
6%
Random Selection
6%
Test Generation Program
6%
Density Functional Theory
6%
System Clock
6%
Propagation Delay
6%
Combinational Logic Network
6%
Preprocessor
6%
Synthesis Algorithm
6%
Test Application Time
6%
Power Dissipation
6%
Good Performance
6%
Complementary Metal Oxide Semiconductor
6%
Testing Process
6%
Indeterminates
6%
