• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1977 …2006

Research activity per year

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  • 2006

    BIST pretest of ICs: Risks and benefits

    Nakamura, Y., Savir, J. & Fujiwara, H., Nov 22 2006, Proceedings - 24th IEEE VLSI Test Symposium. p. 142-147 6 p. 1617577. (Proceedings of the IEEE VLSI Test Symposium; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Scopus citations
  • 2003

    Efficient LU factorization on FPGA-based machines

    Wang, X., Ziavras, S. G. & Savir, J., Dec 1 2003, Proceedings of the Seventh IASTED International Multi-Conference - Power and Energy Systems. Smedley, K. M. (ed.). p. 459-464 6 p. (Proceedings of the IASTED Multi-Conference- Power and Energy Systems; vol. 7).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2002

    Observer-based test of analog linear time-inv ariant circuits

    Guo, Z. & Savir, J., Jan 1 2002, Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002. Renovell, M., Kajihara, S., Demidenko, S. & Al-Bahadly, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 13-17 5 p. 994581. (Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Scopus citations
  • Test limitations of parametric faults in analog circuits

    Savir, J. & Guo, Z., Jan 1 2002, Proceedings of the 11th Asian Test Symposium, ATS 2002. IEEE Computer Society, p. 39-44 6 p. 1181682. (Proceedings of the Asian Test Symposium; vol. 2002-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Scopus citations
  • 1999

    Memory chip BIST architecture

    Savir, J., Dec 1 1999, Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, p. 384-385 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Scopus citations
  • 1997

    BIST-based fault diagnosis in the presence of embedded memories

    Savir, J., Dec 1 1997, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Anon (ed.). IEEE, p. 37-47 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Scopus citations
  • Random pattern testability of memory control logic

    Savir, J., Jan 1 1997, Proceedings of the IEEE VLSI Test Symposium. Anon (ed.). IEEE, p. 399-407 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Scopus citations
  • Test generators need to be modified to handle CMOS designs

    Savir, J., 1997, IMTC 1997 - IEEE Instrumentation and Measurement Technology Conference: Sensing, Processing, Networking, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1436-1441 6 p. 612437. (Conference Record - IEEE Instrumentation and Measurement Technology Conference; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1992

    Developments in delay testing

    Savir, J., 1992, Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992. IEEE Computer Society, p. 247-253 7 p. 232760. (Proceedings of the IEEE VLSI Test Symposium; vol. 1992-April).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Scopus citations
  • Skewed-Load Transition Test: Part II, Coverage

    Patil, S. & Savir, J., Jan 1 1992, Proceedings International Test Conference, ITC 1992. Institute of Electrical and Electronics Engineers Inc., p. 714-722 9 p. 527893. (Proceedings - International Test Conference; vol. 1992-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    62 Scopus citations
  • Skewed-Load Transition Test: Part I, Calculus

    Savir, J., Jan 1 1992, Proceedings International Test Conference, ITC 1992. Institute of Electrical and Electronics Engineers Inc., p. 705-713 9 p. 527892. (Proceedings - International Test Conference; vol. 1992-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    123 Scopus citations
  • 1990

    AC product defect level and yield loss

    Savir, J., Sep 1 1990, Digest of Papers - International Test Conference. Publ by IEEE, p. 726-738 13 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Scopus citations
  • A multiple seed linear feedback shift register

    Savir, J. & McAnney, W. H., Sep 1 1990, Digest of Papers - International Test Conference. Publ by IEEE, p. 657-659 3 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Scopus citations
  • 1989

    Testing for coupled cells in random-access memories

    Savir, J., McAnney, W. H. & Vecchio, S. R., Dec 1 1989, 20 Int Test Conf 1989 ITC. Anon (ed.). Publ by IEEE, p. 439-451 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Scopus citations
  • 1988

    Identification of failing tests with cycling registers

    Savir, J. & McAnney, W. H., Dec 1 1988, Digest of Papers - International Test Conference. Publ by IEEE, p. 322-328 7 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    42 Scopus citations
  • Why partial design verification works better than it should.

    Savir, J., Dec 1 1988, Proceedings - Design Automation Conference. Publ by IEEE, p. 704-707 4 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Scopus citations
  • 1987

    DOUBLE-PARITY SIGNATURE ANALYSIS FOR LSSD NETWORKS.

    Savir, J. & McAnney, W. H., Dec 1 1987, Digest of Papers - International Test Conference. IEEE, p. 510-516 7 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Scopus citations
  • THERE IS INFORMATION IN FAULTY SIGNATURES.

    McAnney, W. H. & Savir, J., Dec 1 1987, Digest of Papers - International Test Conference. IEEE, p. 630-636 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    46 Scopus citations
  • 1986

    BUILT-IN CHECKING OF THE CORRECT SELF-TEST SIGNATURE.

    McAnney, W. H. & Savir, J., Dec 1 1986, Digest of Papers - International Test Conference. IEEE, p. 54-58 5 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Scopus citations
  • RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

    Savir, J. & McAnney, W. H., Dec 1 1986, Digest of Papers - International Test Conference. IEEE, p. 263-273 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    33 Scopus citations
  • 1985

    ON THE MASKING PROBABILITY WITH ONE'S COUNT AND TRANSITION COUNT.

    Savir, J. & McAnney, W. H., Dec 1 1985, Unknown Host Publication Title. IEEE, p. 111-113 3 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Scopus citations
  • RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

    Savir, J., McAnney, W. H. & Vecchio, S. R., Dec 1 1985, Digest of Papers - International Test Conference. IEEE, p. 106-114 9 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Scopus citations
  • RANDOM PATTERN TESTING FOR DATA-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

    McAnney, W. H., Savir, J. & Vecchio, S. R., Dec 1 1985, Digest of Papers - International Test Conference. IEEE, p. 100-105 6 p. (Digest of Papers - International Test Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Scopus citations
  • 1984

    LAYOUT INFLUENCES TESTABILITY.

    Spencer, T. H. & Savir, J., 1984, Unknown Host Publication Title. IEEE, p. 291-295 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1983

    ON RANDOM PATTERN TEST LENGTH.

    Savir, J. & Bardell, P. H., Dec 1 1983, Digest of Papers - International Test Conference. IEEE, p. 95-106 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Scopus citations
  • RANDOM PATTERN TESTABILITY.

    Savir, J., Ditlow, G. & Bardell, P. H., Jan 1 1983, Digest of Papers - FTCS (Fault-Tolerant Computing Symposium). IEEE, p. 80-89 10 p. (Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    24 Scopus citations