Internet of Things (IoT) devices are projected to exceed $1000B by 2025, with a web of interconnection projected to comprise approximately 75+ billion IoT devices. The large number of IoTs consists of sensory imaging systems that enable massive data collection from the environment and people. However, considerable portions of the captured sensory data are redundant and unstructured. Data conversion of such large raw data, storing in volatile memories, transmission, and computation in on-/off-chip processors, impose high energy consumption, latency, and a memory bottleneck at the edge. Moreover, because renewing batteries for IoT devices is very costly and sometimes impracticable, energy harvesting devices with ambient energy sources and low maintenance have impacted a wide range of IoT applications such as wearable devices, smart cities, and the intelligent industry. This project explores and designs new high-speed, low-power, and normally-off computing architectures for resource-limited sensory nodes by exploiting cross-layer post-CMOS approaches to overcome these issues. Successful completion of this research will have benefits to a variety of critical application domains, including medical monitoring, industrial and/or environmental sensors. This project will make a strong effort on developing undergraduate and graduate course modules, propagating transportable and open-source models, and broadening STEM participation through publications/presentations at conferences for knowledge dissemination.This project will follow two main research thrusts. Thrust 1 designs and analyzes a Processing-In-Sensor Unit (PISU) co-integrating always-on sensing and processing capabilities in conjunction with a Processing-Near-Sensor Unit (PNSU). The hybrid platform will feature real-time programmable granularity-configurable arithmetic operations to balance the accuracy, speed, and power-efficiency trade-offs under both continuous and energy-harvesting-powered imaging scenarios. This platform will enable resource-limited edge devices to locally perform data and compute-intensive applications such as machine learning tasks while consuming much less power than present state-of-the-art technology. The power profile of ambient energy sources imposes fundamental constraints on processing stability and duration. To achieve high sensing and computation parallelism under unstable power supply conditions, Intermittent-Robust Integrated Sensing Computation (IRISC) will be designed. During power failure, IRISC stores intermediate values in non-volatile spin-based devices, which will ensure uninterrupted operations. To meet the hardware constraints and mitigate the high write power of spin-based devices, they will be selectively and efficiently inserted within the datapaths through a novel NV-clustering methodology to create corresponding intermittent-robust IP cores that realize intermittent computation with lower power consumption while maintaining middleware coherence. This cross-layer devices-to-system research approach will be assessed by developing a comprehensive evaluation framework, a transportable energy-harvested computational workload suite, and FPGA-MRAM-based emulation platforms for IRISC.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
|Effective start/end date||8/1/22 → 7/31/25|
- National Science Foundation: $279,334.00
Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.