International Symposium on High Dielectric Constant Gate Stacks will be held in Los Angeles, California on October 16-21, 2005.

ECS-0535679 This proposal requests funds to support the International Symposium on HIGH DIELECTRIC CONSTANT GATE STACKS III to be held as part of 208th Meeting of The Electrochemical Society, Inc. Los Angeles, California, October 16-21, 2005. More specifically, the funds requested ($3,955.00) will be utilized for partial support of the travel expenses for up to five deserving graduate/undergraduate students and registration waiver for only 3 invited speakers out of 25 confirmed invited speakers. This symposium will address the fundamental science and recent technologies of advanced gate stacks for complementary metal-oxide-semiconductor (CMOS) and memory applications in sub-65 nm feature size integrated circuits, including: (1) Substrates: Higher mobility semiconductors such as strained Si, Si(110) and (111), SiGe, Ge and III-V compounds, GeOI, GaAs-on-insulator, and SOI. (2) High k Gate Dielectric Materials and Processing: Trends in high k gate dielectric technologies for 65 nm and beyond, novel high k materials, advanced oxynitrides for 65 nm and beyond, high k gate dielectric growth techniques, high k gate dielectric deposition methods, advanced precursors for CVD. (3) Gate Electrode Materials and Processing: Trends in gate electrode technologies for 65 nm and beyond; poly-Si, silicided, and metal gate electrodes, band-edge and midgap work-function materials, gate electrode deposition methods. (4) High K Gate Dielectric Interfaces: Silicon/High-K and High-K/Gate- Electrode Interfaces Oxygen Diffusion and Mechanisms of Interface Layer Formation Interface Preparation, Passivation, Engineering, and Control. (5) Advanced Gate Stack Reliability: Identification of Main Reliability Problems in Low Voltage Application and New Reliability Models Bias Temperature Instability Metallic Cross-Contamination Across Layers Mechanisms of Electron Mobility Degradation Thermal Stability of New Materials. (6) High K Gate Dielectric Characterization and Methodologies: Advanced Physical, Chemical, and Electrical Characterization of Gate Stacks Accurate Determination of Dielectric Capacitance Trap Parameter Extraction Non-Contact Electrical Characterization Work-function Extraction Methodologies Determination of Tunneling Electron/Hole Mass. (7) DRAM and Non-Volatile Memory Materials: Trends in High K DRAM Capacitor Technologies Electrode/Dielectric Chemical Interactions Thermal Stability of Structures Non-Volatile and Novel Memory Applications.