SHF: EAGER: Transactional Processors: Exploiting Hardware Transaction Processing for Reliable Computing

With the semiconductor technology entering the nano-scale era, CMOS devices are facing a dramatic increase in vulnerability to transient faults such as soft errors induced by energetic particle strikes. Such soft errors have become a major challenge in designing next generation microprocessors. While techniques for optimizing reliability at low levels can be accurate, they incur significantly high hardware overheads and costly manufacturing processes. The objective of the proposed EAGER proposal is to explore a new flexible processor architecture for highly effective reliable computing by exploiting the semantics of hardware transaction processing. Instead of simply augmenting existing processors for an attainable reliability, the PI proposes to exploit the semantics of transaction processing from database management systems and recent transactional memories for the design and implementation of the transactional processor architecture, where the reliable computing is an inherent property. The transactional processor aims to provide highly effective and flexible transaction-level verification and native supports for recovery from detected errors. The PI will explore the design space of hardware transaction processing and transaction based reliable computing, as well as new programming language constructs to extend current programming languages for writing programs efficiently in transactions. The success of this project may result in design of low-cost reliable computing platforms based on hardware transaction processing. In addition, the proposed activities will provide a unique channel to attract students from under-represented groups and minorities into science and engineering. The PI plans to take advantage of several college and university wide outreach programs to interact with high school students and teachers to motivate them in computer science.