1/f noise as a tool to assess Fermi level pinning (E_F) at the HfO₂/ poly-Si and FUSI interface in high-κ n-MOSFETs

Evidence is provided that 1/f noise may be useful in the analysis of the traps responsible for Fermi level pinning at the HfO₂/poly-Si or HfO₂/FUSI interface in high-κ n-MOSFETs. As reference devices, transistors with 1.5 nm SiON gate dielectric have been used. It is shown that adding a few (5, 10, 20) monolayers of HfO₂ enhances markedly the normalized noise magnitude in both poly-Si and FUSI devices. The 1/f noise characteristic behaves according to the number fluctuations theory and the results are interpreted in terms of trapping and de-trapping of channel carriers by defects in the gate dielectric layer. Differences in trap densities, derived from the low-frequency noise spectra are noticed at the gate/dielectric interface, which can explain the Fermi-level pinning in these devices. Additionally, it is shown that the correlated mobility fluctuations derived from the 1/f noise at larger gate voltage overdrives correlate well with the low-field mobility of the n-MOSFETs, demonstrating that the same traps in the gate dielectric are also partly responsible for the mobility degradation. Copyright The Electrochemical Society.