Abstract
Nowadays, arithmetic computing is an important subject in computer architectures in which the one-bit full-adder gate plays a significant role. Thus, efficient design of such full-adder component can be beneficial to the overall efficiency of the entire system. In this essay, a novel method for the design and simulation of a combined majority gate toward realization of the one-bit full-adder gate is proposed. We inspect an alternative approach for the streamlined physical design of quantum-dot cellular automata (QCA) full-adder circuits in which the placement of input cells and wire crossing congestion are substantially reduced. The proposed method has outstanding characteristics such as low complexity, reduced area consumption, simplified physical design, and ultra-high speed one-bit full-adder. Based on simulation results the proposed design provides 33.33% reduction in area and 20.00% improvement in complexity as well as 10.49% in 1 Ek reduction in power consumption.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1165-1177 |
| Number of pages | 13 |
| Journal | International Journal of Information Technology (Singapore) |
| Volume | 13 |
| Issue number | 3 |
| DOIs | |
| State | Published - Jun 2021 |
| Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Artificial Intelligence
- Information Systems
- Applied Mathematics
- Electrical and Electronic Engineering
- Computer Networks and Communications
- Computer Science Applications
- Computational Theory and Mathematics
Keywords
- Arithmetic circuit
- Combined majority gate
- Full-adder gate
- Power consumption
- Quantum-dot cellular automata (QCA)