Abstract
The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM) |
| Pages | 3231-3238 |
| Number of pages | 8 |
| Volume | 18 |
| State | Published - Dec 1 2004 |
| Event | Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM) - Santa Fe, NM, United States Duration: Apr 26 2004 → Apr 30 2004 |
Other
| Other | Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM) |
|---|---|
| Country/Territory | United States |
| City | Santa Fe, NM |
| Period | 4/26/04 → 4/30/04 |
All Science Journal Classification (ASJC) codes
- Engineering(all)