@inproceedings{f9ff2d1b27b74b06a7e13f875e06ea53,
title = "A configurable Mu itiprocessor and dynamic load balancing for parallel LU factorization",
abstract = "The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.",
keywords = "Dynamic load balancing, FPGA, LU factorization, Multiprocessor, Parallel processing",
author = "Xiaofang Wang and Ziavras, {Sotirios G.}",
year = "2004",
language = "English (US)",
isbn = "0769521320",
series = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)",
pages = "3231--3238",
booktitle = "Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)",
note = "Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM) ; Conference date: 26-04-2004 Through 30-04-2004",
}