TY - GEN
T1 - A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors
AU - Wang, Xiaofang
AU - Ziavras, Sotirios G.
N1 - Funding Information:
_______________________________ *This work was supported in part by the U.S. Department of Energy under grant DE-FG02-03CH11171.
PY - 2005
Y1 - 2005
N2 - Encouraged by continuous advances in FPGA technologies, we explore high-performance Multi-Processor-on-a-Programmable-Chip (MPoPC) reconfigurable architectures. This paper proposes a methodology for assigning resources at run time and scheduling large-scale floating-point, data-parallel applications on our mixed-mode HERA MPoPC. HERA stands for HEterogeneous Reconfigurable Architecture. An application is represented by a novel mixed-mode task flow graph which is scheduled to run under a variety of independent or cooperating parallel computing modes: SIMD (Single-Instruction, Multiple-Data), Multiple-SIMD and MIMD (Multiple-Instruction, Multiple-Data). The reconfigurable logic is customized at static time and reconfigured at run time to match application characteristics. An in-house developed parallel power flow analysis code by Newton 's method is employed to verify the methodology and evaluate the performance. This application is of utmost importance to any power grid.
AB - Encouraged by continuous advances in FPGA technologies, we explore high-performance Multi-Processor-on-a-Programmable-Chip (MPoPC) reconfigurable architectures. This paper proposes a methodology for assigning resources at run time and scheduling large-scale floating-point, data-parallel applications on our mixed-mode HERA MPoPC. HERA stands for HEterogeneous Reconfigurable Architecture. An application is represented by a novel mixed-mode task flow graph which is scheduled to run under a variety of independent or cooperating parallel computing modes: SIMD (Single-Instruction, Multiple-Data), Multiple-SIMD and MIMD (Multiple-Instruction, Multiple-Data). The reconfigurable logic is customized at static time and reconfigured at run time to match application characteristics. An in-house developed parallel power flow analysis code by Newton 's method is employed to verify the methodology and evaluate the performance. This application is of utmost importance to any power grid.
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U2 - 10.1109/FPT.2005.1568524
DO - 10.1109/FPT.2005.1568524
M3 - Conference contribution
AN - SCOPUS:33745687448
SN - 0780394070
SN - 9780780394070
T3 - Proceedings - 2005 IEEE International Conference on Field Programmable Technology
SP - 51
EP - 58
BT - Proceedings - 2005 IEEE International Conference on Field Programmable Technology
T2 - 2005 IEEE International Conference on Field Programmable Technology
Y2 - 11 December 2005 through 14 December 2005
ER -