A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors

Xiaofang Wang, Sotirios G. Ziavras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Encouraged by continuous advances in FPGA technologies, we explore high-performance Multi-Processor-on-a-Programmable-Chip (MPoPC) reconfigurable architectures. This paper proposes a methodology for assigning resources at run time and scheduling large-scale floating-point, data-parallel applications on our mixed-mode HERA MPoPC. HERA stands for HEterogeneous Reconfigurable Architecture. An application is represented by a novel mixed-mode task flow graph which is scheduled to run under a variety of independent or cooperating parallel computing modes: SIMD (Single-Instruction, Multiple-Data), Multiple-SIMD and MIMD (Multiple-Instruction, Multiple-Data). The reconfigurable logic is customized at static time and reconfigured at run time to match application characteristics. An in-house developed parallel power flow analysis code by Newton 's method is employed to verify the methodology and evaluate the performance. This application is of utmost importance to any power grid.

Original languageEnglish (US)
Title of host publicationProceedings - 2005 IEEE International Conference on Field Programmable Technology
Pages51-58
Number of pages8
DOIs
StatePublished - 2005
Event2005 IEEE International Conference on Field Programmable Technology - , Singapore
Duration: Dec 11 2005Dec 14 2005

Publication series

NameProceedings - 2005 IEEE International Conference on Field Programmable Technology
Volume2005

Other

Other2005 IEEE International Conference on Field Programmable Technology
Country/TerritorySingapore
Period12/11/0512/14/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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