A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors

Keyphrases

• Analysis Code 33%
• Application Characteristics 33%
• Chip multiprocessor 100%
• Computing Mode 33%
• Data-parallel Applications 33%
• Dynamic Resource Assignment 100%
• Dynamic Resource Scheduling 100%
• Floating-point Data 33%
• Flow Graph 33%
• FPGA Technology 33%
• High Performance 33%
• Mixed Mode 100%
• Multiple Data 33%
• Multiprocessor 66%
• Newton's Method 33%
• On chip 100%
• Parallel Computing 33%
• Power Flow Analysis 33%
• Power Grid 33%
• Programmable chip 66%
• Reconfigurable 100%
• Reconfigurable Architectures 66%
• Reconfigurable Logic 33%
• Single Instruction multiple Data 66%
• Static Time 33%
• Task Flow 33%

Computer Science

• Chip Multiprocessor 100%
• Code Analysis 50%
• Floating Point 50%
• multi-processor 100%
• Parallel Application 50%
• Parallel Computing 50%
• reconfigurable architecture 100%
• Reconfigurable Logic 50%
• Single Instruction Multiple Data 100%
• Utmost Importance 50%

Engineering

• Analysis Code 33%
• Field Programmable Gate Arrays 33%
• Floating Point 33%
• Flow Analysis 33%
• Flow Graph 33%
• Mixed Mode 100%
• Multiple Instruction Multiple Data 33%
• Power Flow 33%
• Power Grid 33%
• Single Instruction Multiple Data 66%
• Tasks 33%