Abstract
This paper presents the design of a high-speed digital correlator implemented in a Xilinx field programmable gate array. The theoretical maximum operating frequency of the digital correlator is calculated and simulated to be 40 MHz, a significant speed improvement over commercially available correlators. Implementation results verify this frequency of operation.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 373-381 |
| Number of pages | 9 |
| Journal | International Journal of Electronics |
| Volume | 72 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 1992 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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