A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks

Shaahin Angizi, Mehrdad Morsali, Sepehr Tabrizchi, Arman Roohi

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this work, a high-speed and energy-efficient comparator-based Near-Sensor Local Binary Pattern accelerator architecture (NS-LBP) is proposed to execute a novel local binary pattern deep neural network. First, inspired by recent LBP networks, we design an approximate, hardware-oriented, and multiply-accumulate (MAC)-free network named Ap-LBP for efficient feature extraction, further reducing the computation complexity. Then, we develop NS-LBP as a processing-in-SRAM unit and a parallel in-memory LBP algorithm to process images near the sensor in a cache, remarkably reducing the power consumption of data transmission to an off-chip processor. Our circuit-to-application co-simulation results on MNIST and SVHN datasets demonstrate minor accuracy degradation compared to baseline CNN and LBP-network models, while NS-LBP achieves 1.25 GHz and an energy-efficiency of 37.4 TOPS/W. NS-LBP reduces energy consumption by 2.2× and execution time by a factor of 4× compared to the best recent LBP-based networks.

Original languageEnglish (US)
Pages (from-to)73-83
Number of pages11
JournalIEEE Transactions on Emerging Topics in Computing
Volume12
Issue number1
DOIs
StatePublished - Jan 1 2024

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)
  • Information Systems
  • Human-Computer Interaction
  • Computer Science Applications

Keywords

  • Processing-in-memory
  • SRAM
  • accelerator
  • near-sensor processing

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