A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency

Arman Roohi, Ramtin Zand, Shaahin Angizi, Ronald F. Demara

Research output: Contribution to journalArticlepeer-review

45 Scopus citations

Abstract

A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. Performance of the PPRG design is validated through implementing thirteen standard combinational Boolean functions of three variables, which demonstrate from 10.7 to 41.9 percent improvement over the previous gate counts obtained with other reversible and/or preserving gate designs. Switching and leakage energy dissipation as low as 0.141 eV and 0.294 eV, for 1.5 E-k energy level are achieved using PPRG, respectively. The utility of PPRG is leveraged to design a one-bit full adder with 171 cells occupying only 0.19 \mu \text{m}^2 area. Finally, fault detection and isolation properties are formalized into a concise procedure. PPRG-based circuits capable of self-configuring active recovery for selected three-variable standard functions are realized using a memoryless method irrespective of garbage outputs.

Original languageEnglish (US)
Article number7518653
Pages (from-to)450-459
Number of pages10
JournalIEEE Transactions on Emerging Topics in Computing
Volume6
Issue number4
DOIs
StatePublished - Oct 1 2018
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)
  • Information Systems
  • Human-Computer Interaction
  • Computer Science Applications

Keywords

  • Quantum-dot cellular automata
  • full adder
  • parity-preserving
  • reversible logic
  • self-checking fault detection methodology

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