AC product defect level and yield loss

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Pages726-738
Number of pages13
ISBN (Print)0818620641
StatePublished - Sep 1 1990
Externally publishedYes
EventProceedings - International Test Conference 1990 - Washington, DC, USA
Duration: Sep 10 1990Sep 14 1990

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

Other

OtherProceedings - International Test Conference 1990
CityWashington, DC, USA
Period9/10/909/14/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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