TY - GEN
T1 - AC product defect level and yield loss
AU - Savir, Jacob
PY - 1990/9
Y1 - 1990/9
N2 - The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other.
AB - The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other.
UR - http://www.scopus.com/inward/record.url?scp=0025478889&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0025478889&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0025478889
SN - 0818620641
T3 - Digest of Papers - International Test Conference
SP - 726
EP - 738
BT - Digest of Papers - International Test Conference
PB - Publ by IEEE
T2 - Proceedings - International Test Conference 1990
Y2 - 10 September 1990 through 14 September 1990
ER -