Abstract
The ac defect level and yield loss after test for both logic and random-access memory (RAM) semiconductor chips is considered. Computation of chip ac defect level and yield loss, after test, is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters, or measured by a tester. Both the tester accuracy and the test coverage in computing the ac defect level and yield loss is taken into account.
Original language | English (US) |
---|---|
Pages (from-to) | 195-205 |
Number of pages | 11 |
Journal | IEEE Transactions on Semiconductor Manufacturing |
Volume | 3 |
Issue number | 4 |
DOIs | |
State | Published - Nov 1990 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering
Keywords
- Chip defect level
- ac test
- chip yield
- dc test
- probability density function
- propagation delay