AC Product Defect Level and Yield Loss

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

The ac defect level and yield loss after test for both logic and random-access memory (RAM) semiconductor chips is considered. Computation of chip ac defect level and yield loss, after test, is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters, or measured by a tester. Both the tester accuracy and the test coverage in computing the ac defect level and yield loss is taken into account.

Original languageEnglish (US)
Pages (from-to)195-205
Number of pages11
JournalIEEE Transactions on Semiconductor Manufacturing
Volume3
Issue number4
DOIs
StatePublished - Nov 1990
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Keywords

  • Chip defect level
  • ac test
  • chip yield
  • dc test
  • probability density function
  • propagation delay

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