TY - GEN
T1 - Adaptive scheduling of array-intensive applications on mixed-mode reconfigurable multiprocessors
AU - Wang, Xiaofang
AU - Ziavras, Sotirios G.
PY - 2005
Y1 - 2005
N2 - Array-based applications are normally computation-intensive and many customized designs have been proposed targeting FPGA (Field-Programmable Gate Array) implementations to accelerate their real-time solutions. Most often a time-consuming procedure to convert floating-point representations for a fixed-point implementation is necessary due to insufficient hardware resources. Recent remarkable advances in state-of-the-art FPGAs provide new opportunities. This paper presents a dynamic scheduling strategy that applies novel application characterization and adaptive allocation of processors among the active tasks; we show results for our in-house developed mixed-mode MPoPC (MultipProcessor-on- a-Programmable-Chip) HERA (Heterogeneous Reconfigurable Architecture) machine. The innovative adaptive parallelization technique combined with the unique flexibilities provided by the reconfigurable logic help to achieve high utilization of resources and potentially minimum execution times. Experimental results for parallel Singular Value Decomposition (SVD) on Xilinx Virtex II FPGAs are reported.
AB - Array-based applications are normally computation-intensive and many customized designs have been proposed targeting FPGA (Field-Programmable Gate Array) implementations to accelerate their real-time solutions. Most often a time-consuming procedure to convert floating-point representations for a fixed-point implementation is necessary due to insufficient hardware resources. Recent remarkable advances in state-of-the-art FPGAs provide new opportunities. This paper presents a dynamic scheduling strategy that applies novel application characterization and adaptive allocation of processors among the active tasks; we show results for our in-house developed mixed-mode MPoPC (MultipProcessor-on- a-Programmable-Chip) HERA (Heterogeneous Reconfigurable Architecture) machine. The innovative adaptive parallelization technique combined with the unique flexibilities provided by the reconfigurable logic help to achieve high utilization of resources and potentially minimum execution times. Experimental results for parallel Singular Value Decomposition (SVD) on Xilinx Virtex II FPGAs are reported.
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M3 - Conference contribution
AN - SCOPUS:33847633494
SN - 1424401313
SN - 9781424401314
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1642
EP - 1646
BT - Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers
T2 - 39th Asilomar Conference on Signals, Systems and Computers
Y2 - 28 October 2005 through 1 November 2005
ER -