Array-based applications are normally computation-intensive and many customized designs have been proposed targeting FPGA (Field-Programmable Gate Array) implementations to accelerate their real-time solutions. Most often a time-consuming procedure to convert floating-point representations for a fixed-point implementation is necessary due to insufficient hardware resources. Recent remarkable advances in state-of-the-art FPGAs provide new opportunities. This paper presents a dynamic scheduling strategy that applies novel application characterization and adaptive allocation of processors among the active tasks; we show results for our in-house developed mixed-mode MPoPC (MultipProcessor-on- a-Programmable-Chip) HERA (Heterogeneous Reconfigurable Architecture) machine. The innovative adaptive parallelization technique combined with the unique flexibilities provided by the reconfigurable logic help to achieve high utilization of resources and potentially minimum execution times. Experimental results for parallel Singular Value Decomposition (SVD) on Xilinx Virtex II FPGAs are reported.