An FPGA co-processor implementation of Homomorphic Encryption

David Bruce Cousins, John Golusky, Kurt Rohloff, Daniel Sumorok

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Scopus citations


One of the goals of the DARPA PROCEED pro-gram has been accelerating the development of a practical Fully Homomorphic Encryption (FHE) scheme. For the past three years, this program has succeeded in accelerating various aspects of the FHE concept toward practical implementation and use. FHE is a game-changing technology to enable secure, general computation on encrypted data on untrusted off-site hardware, without the data ever being decrypted for processing. FHE schemes developed under PROCEED have achieved multiple orders of magnitude improvement in computation, but further means of acceleration, such as implementations on specialized hardware, such as an FPGA can improve the speed of computa-tion even further. The current interest in FHE computation resulted from breakthroughs demonstrating the existence of FHE schemes [1, 2] that allowed arbitrary computation on encrypted data. Specif-ically, our contribution to the Proceed program has been the development of FPGA based hardware primitives to accelerate the computation on encrypted data using an FHE cryptosystem based on NTRU-like lattice techniques [3] with additional with additional support for efficient key switching and modulus re-duction operations to reduce the frequency of bootstrapping op-erations [4]. Cipher texts in our scheme are represented as rec-tangular matrices of 64-bit integers. This bounding of the oper-and sizes has allowed us to take advantage of modern code gen-eration tools developed by Mathworks to implement VHDL code for FPGA circuits directly from Simulink models. Furthermore the implicit parallelism of the scheme allows for large amounts of pipelining in the implementation in order to achieve efficient throughput. The resulting VHDL is integrated into an AXI4 bus 'Soft System on Chip' using Xilinx platform studio and a Mi-croblaze soft core processor running on aVirtex7 VC707 evalua-tion board. This report presents new Simulink primitives that had to be developed to deal with these new requirements.

Original languageEnglish (US)
Title of host publication2014 IEEE High Performance Extreme Computing Conference, HPEC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962334
StatePublished - Feb 11 2014
Externally publishedYes
Event2014 IEEE High Performance Extreme Computing Conference, HPEC 2014 - Waltham, United States
Duration: Sep 9 2014Sep 11 2014

Publication series

Name2014 IEEE High Performance Extreme Computing Conference, HPEC 2014


Other2014 IEEE High Performance Extreme Computing Conference, HPEC 2014
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Software


  • Co-processor
  • FPGA
  • Fully Homomorphic Encryption


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