Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Roberto Rojas-Cessa; Ziqian Dong

Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Roberto Rojas-Cessa (Inventor), Ziqian Dong (Inventor)

New Jersey Institute of Technology

Research output: Innovation › Patent

Abstract

https://www.google.com/patents/US8675673

Original language	English (US)
State	Published - Jul 2018

Keywords

Patent Issued

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title = "Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.",

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AU - Dong, Ziqian

PY - 2018/7

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N2 - https://www.google.com/patents/US8675673

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Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Abstract

Keywords

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