Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Roberto Rojas-Cessa (Inventor), Ziqian Dong (Inventor)

Research output: InnovationPatent

Abstract

https://www.google.com/patents/US8675673

Original languageEnglish (US)
StatePublished - Jul 2018

Keywords

  • Patent Issued

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