Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Roberto Rojas-Cessa; Ziqian Dong

Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Roberto Rojas-Cessa (Inventor)
, Ziqian Dong (Inventor)

New Jersey Institute of Technology

Research output: Innovation › Patent

Abstract

https://www.google.com/patents/US8675673

Original language	English (US)
State	Published - Jul 2018

Keywords

Patent Issued

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@misc{a4eea4b9d951486c95d40799d0b75535,

title = "Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.",

abstract = "https://www.google.com/patents/US8675673",

keywords = "Patent Issued",

author = "Roberto Rojas-Cessa and Ziqian Dong",

year = "2018",

month = jul,

language = "English (US)",

type = "Patent",

}

TY - PAT

T1 - Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

AU - Rojas-Cessa, Roberto

AU - Dong, Ziqian

PY - 2018/7

Y1 - 2018/7

N2 - https://www.google.com/patents/US8675673

AB - https://www.google.com/patents/US8675673

KW - Patent Issued

UR - http://njit.technologypublisher.com/technology/28238

M3 - Patent

ER -

Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.

Abstract

Keywords

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