@inproceedings{9c55ffc107ba493e9275b8aa3385964c,
title = "ASIC design of shared vector accelerators for multicore processors",
abstract = "Vector coprocessor (VP) resources are often underutilized due to the lack of sustained DLP (data-level parallelism) or the presence of vector-length variations in application code. Our work is motivated by: a) the omnipresence of vector operations in high-performance scientific and embedded applications, b) the need for performance and energy efficiency, and c) applications that must often handle various vector sizes. Our design for VP sharing in multicores enhances performance while maintaining low area and energy costs. Our 40nm ASIC design yields 16.66 GFLOPs/Watt. Also, a detailed clock and power gating analysis further proves the viability of our approach.",
keywords = "ASIC design, multicore processor, power management, vector processor",
author = "Beldianu, {Spiridon F.} and Ziavras, {Sotirios G.}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 26th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014 ; Conference date: 22-10-2014 Through 24-10-2014",
year = "2014",
month = dec,
day = "1",
doi = "10.1109/SBAC-PAD.2014.13",
language = "English (US)",
series = "Proceedings - Symposium on Computer Architecture and High Performance Computing",
publisher = "IEEE Computer Society",
pages = "182--189",
booktitle = "Proceedings - IEEE 26th International Symposium",
address = "United States",
}