ASIC design of shared vector accelerators for multicore processors

Spiridon F. Beldianu, Sotirios G. Ziavras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Vector coprocessor (VP) resources are often underutilized due to the lack of sustained DLP (data-level parallelism) or the presence of vector-length variations in application code. Our work is motivated by: a) the omnipresence of vector operations in high-performance scientific and embedded applications, b) the need for performance and energy efficiency, and c) applications that must often handle various vector sizes. Our design for VP sharing in multicores enhances performance while maintaining low area and energy costs. Our 40nm ASIC design yields 16.66 GFLOPs/Watt. Also, a detailed clock and power gating analysis further proves the viability of our approach.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 26th International Symposium
PublisherIEEE Computer Society
Pages182-189
Number of pages8
ISBN (Electronic)9781479969043
DOIs
StatePublished - Dec 1 2014
Event26th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014 - Paris, France
Duration: Oct 22 2014Oct 24 2014

Publication series

NameProceedings - Symposium on Computer Architecture and High Performance Computing
ISSN (Print)1550-6533

Other

Other26th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014
CountryFrance
CityParis
Period10/22/1410/24/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Keywords

  • ASIC design
  • multicore processor
  • power management
  • vector processor

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