Asymmetrically banked value-aware register files

Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined super-scalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and power-efficient register file designs. The register bit-widths of different banks in our AB-VARF register files are specifically customized to capture different narrow-width values. Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. Our experimental evaluation with SPEC CINT2000 benchmark suites shows that AB-VARF reduces the energy consumption by 92.6% over a conventional register file, on the average, at the cost of a 6.6% performance loss to an ideal 1-cycle monolithic register file.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging VLSI Technologies and Architectures
Pages363-368
Number of pages6
DOIs
StatePublished - 2007
EventIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil
Duration: Mar 9 2007Mar 11 2007

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Other

OtherIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/TerritoryBrazil
CityPorto Alegre
Period3/9/073/11/07

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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