BIST analysis of an embedded memory associated logic

Research output: Contribution to journalArticlepeer-review

Abstract

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

Original languageEnglish (US)
Pages (from-to)563-578
Number of pages16
JournalVLSI Design
Volume12
Issue number4
DOIs
StatePublished - 2001

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Keywords

  • Detection probability
  • Exposure probability
  • Markov chain
  • Random patterns
  • Signal probability

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