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BIST analysis of an embedded memory associated logic
J. Savir
Electrical and Computer Engineering
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Keyphrases
Built-in-self-test (BiST)
100%
Embedded Memory
100%
Design Rules
100%
Testability
100%
Circuitry
50%
Flexible Design
50%
Detection Probability
50%
Cutting Algorithm
50%
Test Design
50%
Control Logic
50%
Auxiliary Circuit
50%
Two-port
50%
Feedforward Connections
50%
No Feedback
50%
Engineering
Built-in Self Test
100%
Design Rule
100%
Testability
100%
Test Analysis
100%
Simulation Tool
50%
Feedforward
50%
Detection Probability
50%
Control Logic
50%
Data Path
50%
Useful Work
50%
Computer Science
embedded memory
100%
build-in self-test
100%
Surrounding Logic
100%
Detection Probability
50%
Random Pattern
50%
Simulation Tool
50%
Mathematics
Random Pattern
100%
Detection Probability
100%
Address Input
100%
Material Science
Electronic Circuit
100%