BIST-based fault diagnosis in the presence of embedded memories

Research output: Contribution to journalArticlepeer-review


An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

Original languageEnglish (US)
Pages (from-to)487-500
Number of pages14
JournalVLSI Design
Issue number4
StatePublished - 2001

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


  • Built-in Self-Test (BIST)
  • Fault detection
  • Fault diagnosis
  • Fault simulation
  • Multiple-Input Shift Register (MISR)
  • Signature


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