BIST-based fault diagnosis in the presence of embedded memories

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages37-47
Number of pages11
StatePublished - Dec 1 1997
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: Oct 12 1997Oct 15 1997

Other

OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period10/12/9710/15/97

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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