Abstract
An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.
| Original language | English (US) |
|---|---|
| Pages | 37-47 |
| Number of pages | 11 |
| State | Published - 1997 |
| Event | Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA Duration: Oct 12 1997 → Oct 15 1997 |
Other
| Other | Proceedings of the 1997 International Conference on Computer Design |
|---|---|
| City | Austin, TX, USA |
| Period | 10/12/97 → 10/15/97 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering