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BIST-based fault diagnosis in the presence of embedded memories
J. Savir
Electrical and Computer Engineering
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Keyphrases
Fault Diagnosis
100%
Embedded Memory
100%
Generation Method
50%
Diagnostic Challenge
50%
Fault Simulation
50%
Table-driven
50%
Special Techniques
50%
Fault-free
50%
Test Case Generation
50%
Event Table
50%
Memory Address
50%
Memory Control
50%
Computer Science
embedded memory
100%
Fault Diagnosis
100%
Fault Simulation
50%