BIST diagnostics, Part 1: Simulation models

Research output: Contribution to journalConference articlepeer-review


An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use the combinational logic (i.e., the memory is removed).

Original languageEnglish (US)
Pages (from-to)8-14
Number of pages7
JournalProceedings of the Asian Test Symposium
StatePublished - 1998
EventProceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore
Duration: Dec 2 1998Dec 4 1998

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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