Abstract
An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use the combinational logic (i.e., the memory is removed).
| Original language | English (US) |
|---|---|
| Pages (from-to) | 8-14 |
| Number of pages | 7 |
| Journal | Proceedings of the Asian Test Symposium |
| State | Published - 1998 |
| Event | Proceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore Duration: Dec 2 1998 → Dec 4 1998 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering