BIST pretest of ICs: Risks and benefits

Yoshiyuki Nakamura; Jacob Savir; Hideo Fujiwara

doi:10.1109/VTS.2006.23

BIST pretest of ICs: Risks and benefits

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worth-while performing. As the study shows, in many cases the potential benefits outweigh any potential risks.

Original language	English (US)
Title of host publication	Proceedings - 24th IEEE VLSI Test Symposium
Pages	142-147
Number of pages	6
DOIs	https://doi.org/10.1109/VTS.2006.23
State	Published - 2006
Event	24th IEEE VLSI Test Symposium - Berkeley, CA, United States Duration: Apr 30 2006 → May 4 2006

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2006

Other

Other	24th IEEE VLSI Test Symposium
Country/Territory	United States
City	Berkeley, CA
Period	4/30/06 → 5/4/06

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTS.2006.23

Cite this

@inproceedings{800c78e1281c423b9c7fdb84c392c19b,

title = "BIST pretest of ICs: Risks and benefits",

abstract = "The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worth-while performing. As the study shows, in many cases the potential benefits outweigh any potential risks.",

author = "Yoshiyuki Nakamura and Jacob Savir and Hideo Fujiwara",

year = "2006",

doi = "10.1109/VTS.2006.23",

language = "English (US)",

isbn = "0769525148",

series = "Proceedings of the IEEE VLSI Test Symposium",

pages = "142--147",

booktitle = "Proceedings - 24th IEEE VLSI Test Symposium",

note = "24th IEEE VLSI Test Symposium ; Conference date: 30-04-2006 Through 04-05-2006",

}

TY - GEN

T1 - BIST pretest of ICs

T2 - 24th IEEE VLSI Test Symposium

AU - Nakamura, Yoshiyuki

AU - Savir, Jacob

AU - Fujiwara, Hideo

PY - 2006

Y1 - 2006

N2 - The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worth-while performing. As the study shows, in many cases the potential benefits outweigh any potential risks.

AB - The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worth-while performing. As the study shows, in many cases the potential benefits outweigh any potential risks.

UR - http://www.scopus.com/inward/record.url?scp=33751081853&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33751081853&partnerID=8YFLogxK

U2 - 10.1109/VTS.2006.23

DO - 10.1109/VTS.2006.23

M3 - Conference contribution

AN - SCOPUS:33751081853

SN - 0769525148

SN - 9780769525143

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 142

EP - 147

BT - Proceedings - 24th IEEE VLSI Test Symposium

Y2 - 30 April 2006 through 4 May 2006

ER -

BIST pretest of ICs: Risks and benefits

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this