BIST pretest of ICs: Risks and benefits

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worth-while performing. As the study shows, in many cases the potential benefits outweigh any potential risks.

Original languageEnglish (US)
Title of host publicationProceedings - 24th IEEE VLSI Test Symposium
Pages142-147
Number of pages6
DOIs
StatePublished - Nov 22 2006
Event24th IEEE VLSI Test Symposium - Berkeley, CA, United States
Duration: Apr 30 2006May 4 2006

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2006

Other

Other24th IEEE VLSI Test Symposium
CountryUnited States
CityBerkeley, CA
Period4/30/065/4/06

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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