Breakdown characteristics of high-K gate dielectrics with metal gates

N. Rahim, D. Misra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Considering the breakdown mechanisms of high-k and interfacial (IL) layers are different at higher temperatures than at room temperature, in this work the temperature dependence of stress induced leakage current (SILC) and time dependent dielectric breakdown (TDDB) of theses layers are studied separately. As observed from the low voltage SILC, the interfacial layer initiates the gate stack breakdown process at elevated temperature which is followed by the high-k layer. Activation energy extracted from Weibulll distribution of time-to-breakdown (TBD) data from high-k layer further suggests that the gate stack breakdown occurs when high-k layer ultimately breaks down.

Original languageEnglish (US)
Title of host publicationECS Transactions - Dielectrics for Nanosystems 3
Subtitle of host publicationMaterials Science, Processing, Reliability, and Manufacturing
Pages91-97
Number of pages7
Edition2
DOIs
StatePublished - Nov 17 2008
Event3rd International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 213th ECS Meeting - Phoenix, AZ, United States
Duration: May 18 2008May 22 2008

Publication series

NameECS Transactions
Number2
Volume13
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other3rd International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 213th ECS Meeting
CountryUnited States
CityPhoenix, AZ
Period5/18/085/22/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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