@inproceedings{77e284a3bd344324b7e94d6b798e5e54,
title = "Breakdown characteristics of high-K gate dielectrics with metal gates",
abstract = "Considering the breakdown mechanisms of high-k and interfacial (IL) layers are different at higher temperatures than at room temperature, in this work the temperature dependence of stress induced leakage current (SILC) and time dependent dielectric breakdown (TDDB) of theses layers are studied separately. As observed from the low voltage SILC, the interfacial layer initiates the gate stack breakdown process at elevated temperature which is followed by the high-k layer. Activation energy extracted from Weibulll distribution of time-to-breakdown (TBD) data from high-k layer further suggests that the gate stack breakdown occurs when high-k layer ultimately breaks down.",
author = "N. Rahim and D. Misra",
year = "2008",
doi = "10.1149/1.2908621",
language = "English (US)",
isbn = "9781566776271",
series = "ECS Transactions",
number = "2",
pages = "91--97",
booktitle = "ECS Transactions - Dielectrics for Nanosystems 3",
edition = "2",
note = "3rd International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 213th ECS Meeting ; Conference date: 18-05-2008 Through 22-05-2008",
}