Breakdown characteristics of high-k gate dielectrics with metal gates

D. Misra, N. A. Chowdhury, G. Bersuker, C. Young, R. Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work examines the inherent asymmetry on breakdown characteristics of interfacial layer (IL) and high-κ layer in the overall gate stacks breakdown. Ramped and constant voltage stresses were applied on atomic layer deposited TiN/HfO2/SiO2 gate stacks. Under ramped stress when a thin high-κ layer (≤, 3.3 nm) is used, IL is responsible for the overall gate stack breakdown otherwise the breakdown is initiated by the high-κ layer. Under constant voltage stress the gate stack went through many degradation mechanisms such as charge trapping and defect generation, soft breakdown, progressive breakdown and finally hard breakdown. When the breakdown field of ILs, grown on various process conditions is compared, it was observed that for a fixed IL thickness, breakdown field does not depend on predeposition surface treatment rather it is a function of the quality of IL. Stress-induced leakage current was also studied to correlate with the breakdown behavior.

Original languageEnglish (US)
Title of host publicationECS Transactions - 5th International Symposium on ULSI Process Integration
Pages143-160
Number of pages18
Edition6
DOIs
StatePublished - Dec 1 2007
Event5th International Symposium on ULSI Process Integration - 212th ECS Meeting - Washington, DC, United States
Duration: Oct 7 2007Oct 12 2007

Publication series

NameECS Transactions
Number6
Volume11
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other5th International Symposium on ULSI Process Integration - 212th ECS Meeting
CountryUnited States
CityWashington, DC
Period10/7/0710/12/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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