Charge trapping in high-Κ gate dielectrics: A recent understanding

Charge trapping in Hf-based high-κ dielectrics, used in MOS transistor gate stacks, causes threshold voltage shift (ΔV _T) during constant voltage stress (CVS). It seemed to be very transient due to the presence of a large number of shallow traps and can be eliminated by applying a reverse direction electric field. Recent findings, however, suggest that deep traps significantly contribute to the reliability of various Hf-based high-κ gate stacks. The origin of the deep traps and their dependence on O vacancy formation during dielectric deposition is discussed. ΔV _FB and leakage current dependence on these deep traps is also outlined. It is shown that trapping at deep levels inhibits fast ΔV _T recovery. We have experimentally observed trap levels from low temperature measurements assuring the presence of O vacancies in Hf-silicate based films. Substrate hot electron (SHE) injection gives rise to significant electron trapping and slow post-stress recovery under 'negative bias' conditions, which confirms that O vacancy induced deep defects determine the transient behavior in Hf-silicate based high-κ gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant ΔV _FB. This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics. Copyright The Electrochemical Society.