Clock and data recovery IC for 40 Gb/s fiber-optic receiver

G. Georgiou, Y. Baeyens, Y. K. Chen, C. Groepper, P. Paschke, R. Pullela, M. Reinhold, C. Dorschky, J. P. Mattia, T. W. Von Mohrenfels, C. Schulien

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

Integrated clock data recovery (CDR) circuit is a key element for broad band optical communication systems at 40 Gb/s. We report a 40Gb/s CDR fabricated in Indium-Phosphide heterojunction bipolar transistor (InP HBT) technology using the more robust architecture of a phase lock loop with a digital early-late phase detector. The faster (compared to SiGe) InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This in turn, reduces the circuit complexity (transistor count) and VCO requirements. The integrated IC includes an on-chip LC VCO and on-chip clock dividers to drive an external DEMUX and low frequency PLL control loop. On-chip limiting amplifier buffers are included for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed signal IC operating at the clock rate of 40 GHz. Below, we describe the chip architecture and measurement results.

Original languageEnglish (US)
Pages93-96
Number of pages4
StatePublished - Jan 1 2001
Externally publishedYes
Event23rd Annual GaAs IC Symposium 2001 - Baltimore, MD, United States
Duration: Oct 21 2001Oct 24 2001

Other

Other23rd Annual GaAs IC Symposium 2001
Country/TerritoryUnited States
CityBaltimore, MD
Period10/21/0110/24/01

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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