Clock and data recovery IC for 40 Gb/s fiber-optic receiver

Integrated clock data recovery (CDR) circuit is a key element for broad band optical communication systems at 40 Gb/s. We report a 40Gb/s CDR fabricated in Indium-Phosphide heterojunction bipolar transistor (InP HBT) technology using the more robust architecture of a phase lock loop with a digital early-late phase detector. The faster (compared to SiGe) InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This in turn, reduces the circuit complexity (transistor count) and VCO requirements. The integrated IC includes an on-chip LC VCO and on-chip clock dividers to drive an external DEMUX and low frequency PLL control loop. On-chip limiting amplifier buffers are included for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed signal IC operating at the clock rate of 40 GHz. Below, we describe the chip architecture and measurement results.