Clock and data recovery IC for 40-Gb/s fiber-optic receiver

George Georgiou; Yves Baeyens; Young Kai Chen; Alan H. Gnauck; Garsten Cropper; Peter Paschke; Rajasekhar Pullela; Mario Reinhold; Claus Dorschky; John Paul Mattia; Timo Winkler Von Mohrenfels; Christoph Schuhen

doi:10.1109/JSSC.2002.801186

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

George Georgiou, Yves Baeyens, Young Kai Chen, Alan H. Gnauck, Garsten Cropper, Peter Paschke, Rajasekhar Pullela, Mario Reinhold, Claus Dorschky, John Paul Mattia, Timo Winkler Von Mohrenfels, Christoph Schuhen

Research output: Contribution to journal › Conference article › peer-review

27 Scopus citations

Abstract

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

Original language	English (US)
Pages (from-to)	1120-1125
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	37
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2002.801186
State	Published - Sep 2002
Externally published	Yes
Event	23rd IEEE GaAs IC Symposium - Baltimore, MD, United States Duration: Oct 21 2001 → Oct 24 2001

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Keywords

CDR
Clock and data recovery
Fiber-optic communication receiver
InP HBT
Limiting amplifier
Phase detector
VCO

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10.1109/JSSC.2002.801186

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title = "Clock and data recovery IC for 40-Gb/s fiber-optic receiver",

abstract = "The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.",

keywords = "CDR, Clock and data recovery, Fiber-optic communication receiver, InP HBT, Limiting amplifier, Phase detector, VCO",

author = "George Georgiou and Yves Baeyens and Chen, {Young Kai} and Gnauck, {Alan H.} and Garsten Cropper and Peter Paschke and Rajasekhar Pullela and Mario Reinhold and Claus Dorschky and Mattia, {John Paul} and {Von Mohrenfels}, {Timo Winkler} and Christoph Schuhen",

year = "2002",

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doi = "10.1109/JSSC.2002.801186",

language = "English (US)",

volume = "37",

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number = "9",

note = "23rd IEEE GaAs IC Symposium ; Conference date: 21-10-2001 Through 24-10-2001",

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T1 - Clock and data recovery IC for 40-Gb/s fiber-optic receiver

AU - Georgiou, George

AU - Baeyens, Yves

AU - Chen, Young Kai

AU - Gnauck, Alan H.

AU - Cropper, Garsten

AU - Paschke, Peter

AU - Pullela, Rajasekhar

AU - Reinhold, Mario

AU - Dorschky, Claus

AU - Mattia, John Paul

AU - Von Mohrenfels, Timo Winkler

AU - Schuhen, Christoph

PY - 2002/9

Y1 - 2002/9

N2 - The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

AB - The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

KW - CDR

KW - Clock and data recovery

KW - Fiber-optic communication receiver

KW - InP HBT

KW - Limiting amplifier

KW - Phase detector

KW - VCO

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ER -

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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