Clock and data recovery IC for 40-Gb/s fiber-optic receiver

George Georgiou, Yves Baeyens, Young Kai Chen, Alan H. Gnauck, Garsten Cropper, Peter Paschke, Rajasekhar Pullela, Mario Reinhold, Claus Dorschky, John Paul Mattia, Timo Winkler Von Mohrenfels, Christoph Schuhen

Research output: Contribution to journalConference articlepeer-review

27 Scopus citations


The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

Original languageEnglish (US)
Pages (from-to)1120-1125
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number9
StatePublished - Sep 2002
Externally publishedYes
Event23rd IEEE GaAs IC Symposium - Baltimore, MD, United States
Duration: Oct 21 2001Oct 24 2001

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


  • CDR
  • Clock and data recovery
  • Fiber-optic communication receiver
  • InP HBT
  • Limiting amplifier
  • Phase detector
  • VCO


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