Clock and data recovery ic for 40-Gb/s fiber-optic receiver

George Georgiou; Yves Baeyens; Young Kai Chen; Alan H. Gnauck; Carsten Gropper; Peter Paschke; Rajasekhar Pullela; Mario Reinhold; Claus Dorschky; John Paul Mattia; Timo Winkler Von Mohrenfels; Christoph Schulien

doi:10.1109/9780470545492.ch87

Clock and data recovery ic for 40-Gb/s fiber-optic receiver

George Georgiou, Yves Baeyens, Young Kai Chen, Alan H. Gnauck, Carsten Gropper, Peter Paschke, Rajasekhar Pullela, Mario Reinhold, Claus Dorschky, John Paul Mattia, Timo Winkler Von Mohrenfels, Christoph Schulien

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

Original language	English (US)
Title of host publication	Phase-Locking in High-Performance Systems
Subtitle of host publication	From Devices to Architectures
Publisher	Wiley-IEEE Press
Pages	707-711
Number of pages	5
ISBN (Electronic)	9780470545492
ISBN (Print)	0471447277, 9780471447276
DOIs	https://doi.org/10.1109/9780470545492.ch87
State	Published - Jan 1 2003
Externally published	Yes

All Science Journal Classification (ASJC) codes

General Engineering
General Computer Science

Keywords

Clocks
Integrated circuits
Integrated optics
Optical amplifiers
Optical fiber communication
Transistors
Voltage-controlled oscillators

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10.1109/9780470545492.ch87

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Georgiou, G., Baeyens, Y., Chen, Y. K., Gnauck, A. H., Gropper, C., Paschke, P., Pullela, R., Reinhold, M., Dorschky, C., Mattia, J. P., Von Mohrenfels, T. W., & Schulien, C. (2003). Clock and data recovery ic for 40-Gb/s fiber-optic receiver. In Phase-Locking in High-Performance Systems: From Devices to Architectures (pp. 707-711). Wiley-IEEE Press. https://doi.org/10.1109/9780470545492.ch87

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title = "Clock and data recovery ic for 40-Gb/s fiber-optic receiver",

abstract = "The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.",

keywords = "Clocks, Integrated circuits, Integrated optics, Optical amplifiers, Optical fiber communication, Transistors, Voltage-controlled oscillators",

author = "George Georgiou and Yves Baeyens and Chen, {Young Kai} and Gnauck, {Alan H.} and Carsten Gropper and Peter Paschke and Rajasekhar Pullela and Mario Reinhold and Claus Dorschky and Mattia, {John Paul} and {Von Mohrenfels}, {Timo Winkler} and Christoph Schulien",

year = "2003",

month = jan,

day = "1",

doi = "10.1109/9780470545492.ch87",

language = "English (US)",

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Georgiou, G, Baeyens, Y, Chen, YK, Gnauck, AH, Gropper, C, Paschke, P, Pullela, R, Reinhold, M, Dorschky, C, Mattia, JP, Von Mohrenfels, TW & Schulien, C 2003, Clock and data recovery ic for 40-Gb/s fiber-optic receiver. in Phase-Locking in High-Performance Systems: From Devices to Architectures. Wiley-IEEE Press, pp. 707-711. https://doi.org/10.1109/9780470545492.ch87

TY - CHAP

T1 - Clock and data recovery ic for 40-Gb/s fiber-optic receiver

AU - Georgiou, George

AU - Baeyens, Yves

AU - Chen, Young Kai

AU - Gnauck, Alan H.

AU - Gropper, Carsten

AU - Paschke, Peter

AU - Pullela, Rajasekhar

AU - Reinhold, Mario

AU - Dorschky, Claus

AU - Mattia, John Paul

AU - Von Mohrenfels, Timo Winkler

AU - Schulien, Christoph

PY - 2003/1/1

Y1 - 2003/1/1

N2 - The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

AB - The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

KW - Clocks

KW - Integrated circuits

KW - Integrated optics

KW - Optical amplifiers

KW - Optical fiber communication

KW - Transistors

KW - Voltage-controlled oscillators

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SN - 0471447277

SN - 9780471447276

SP - 707

EP - 711

BT - Phase-Locking in High-Performance Systems

PB - Wiley-IEEE Press

ER -

Clock and data recovery ic for 40-Gb/s fiber-optic receiver

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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