Clock and data recovery ic for 40-Gb/s fiber-optic receiver

George Georgiou, Yves Baeyens, Young Kai Chen, Alan H. Gnauck, Carsten Gropper, Peter Paschke, Rajasekhar Pullela, Mario Reinhold, Claus Dorschky, John Paul Mattia, Timo Winkler Von Mohrenfels, Christoph Schulien

Research output: Chapter in Book/Report/Conference proceedingChapter


The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gbls. We report a 40-Gb/s CDR fabricated in indium-phosphide heteroJunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in tum, reduces the circuit complexity (transistor count) and the vollage-eontrolled oscillator (YCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an extemal demultiplexer, and low-frequency PLL control loop and on-chip Umiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

Original languageEnglish (US)
Title of host publicationPhase-Locking in High-Performance Systems
Subtitle of host publicationFrom Devices to Architectures
PublisherWiley-IEEE Press
Number of pages5
ISBN (Electronic)9780470545492
ISBN (Print)0471447277, 9780471447276
StatePublished - Jan 1 2003
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • General Engineering
  • General Computer Science


  • Clocks
  • Integrated circuits
  • Integrated optics
  • Optical amplifiers
  • Optical fiber communication
  • Transistors
  • Voltage-controlled oscillators


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