Closing the Loop in LLM-Based Hardware Generation: An Autonomous Agentic Workflow for Robust TPU Design

Large language models (LLMs) can generate hardware description language (HDL) code from high-level specifications, but most existing approaches remain open loop and require manual recovery when designs fail in simulation, verification, or implementation. This limitation is especially severe for approximate arithmetic, where circuits must satisfy both numerical error bounds and architecture-level constraints. We present ARCADE, a separation-enforced multi-agent framework for architecture-aware generation of approximate arithmetic units. ARCADE combines an independent Design Agent and Verifier Agent, a fixed golden-reference NMED harness for functional acceptance, retrieval-augmented error memory (RAEM) for closed-loop repair, and automated integration into an RTL-to-GDSII flow. Evaluated on 13 approximate-adder specifications within the APTPU datapath, ARCADE improves first-attempt success from 30.8% to 76.9%, solves all specifications within three attempts, and reduces average NMED from 25.6% to 0.7%. The framework and code will be released as open source at https://github.com/ACADLab/ARCADE.