CMOS transistor processing compatible with monolithic 3-D integration

B. Rajendran, R. S. Shenoy, D. J. Witte, N. S. Chokshi, R. L. DeLeon, G. S. Tompa, R. F.W. Pease

Research output: Contribution to conferencePaperpeer-review

5 Scopus citations

Abstract

Laser annealing can be used for electrical activation of dopants without excessively heating material deeper within the work piece. In an earlier work, we demonstrated that laser annealing could be used for activating dopants in the upper levels of an exemplary three-dimensional (3D) integrated circuit structure without affecting the reliability of the devices below. Here, we demonstrate a process for fabricating good quality CMOS transistors by replacing the two critical high temperature steps needed to fabricate transistors in a conventional CMOS process - gate oxidation and source/drain dopant activation - by a 450 °C Low Temperature Oxide (LTO) deposition process and Laser annealing respectively. This process can be used to fabricate transistors on the upper levels of a general 3D IC structure without affecting the reliability of devices below.

Original languageEnglish (US)
Pages76-82
Number of pages7
StatePublished - Dec 1 2005
Externally publishedYes
Event22nd International VLSI Multilevel Interconnection Conference, VMIC 2005 - Fremont, CA, United States
Duration: Oct 4 2005Oct 6 2005

Other

Other22nd International VLSI Multilevel Interconnection Conference, VMIC 2005
Country/TerritoryUnited States
CityFremont, CA
Period10/4/0510/6/05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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