@inproceedings{c0dcdbdc79ac4fb4a8cd9f370fee6ca0,
title = "Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges",
abstract = "Digital Processing-in-Memory (PIM) architectures have recently unleashed significant potential in Deep Neural Network (DNN) acceleration not only by addressing memory-wall bottlenecks but also by offering impressive performance improvement compared to the von-Neumann architecture. Different flavors of DNN ASIC accelerators have also been developed and fabricated, with remarkable performance and efficiency. This paper conducts a comparative study of PIM and Gemmini-generated accelerators for low-bit-width DNN inference and underscores their key architectural constraints, opportunities, and security challenges. To this end, we compare multiple low-power accelerators with our recently taped-out PIM macro to provide a guideline for the community.",
keywords = "ASIC, accelerator, processing-in-memory",
author = "Deepak Vungarala and Mehrdad Morsali and Sepehr Tabrizchi and Arman Roohi and Shaahin Angizi",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 ; Conference date: 06-08-2023 Through 09-08-2023",
year = "2023",
doi = "10.1109/MWSCAS57524.2023.10405996",
language = "English (US)",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "797--800",
booktitle = "2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023",
address = "United States",
}