Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges

Deepak Vungarala, Mehrdad Morsali, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Digital Processing-in-Memory (PIM) architectures have recently unleashed significant potential in Deep Neural Network (DNN) acceleration not only by addressing memory-wall bottlenecks but also by offering impressive performance improvement compared to the von-Neumann architecture. Different flavors of DNN ASIC accelerators have also been developed and fabricated, with remarkable performance and efficiency. This paper conducts a comparative study of PIM and Gemmini-generated accelerators for low-bit-width DNN inference and underscores their key architectural constraints, opportunities, and security challenges. To this end, we compare multiple low-power accelerators with our recently taped-out PIM macro to provide a guideline for the community.

Original languageEnglish (US)
Title of host publication2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages797-800
Number of pages4
ISBN (Electronic)9798350302103
DOIs
StatePublished - 2023
Event2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 - Tempe, United States
Duration: Aug 6 2023Aug 9 2023

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Country/TerritoryUnited States
CityTempe
Period8/6/238/9/23

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Keywords

  • accelerator
  • ASIC
  • processing-in-memory

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