Constraint-based placement and routing for FPGAs using self-organizing maps

Michail Maniatakos, Songhua Xu, Willard L. Miranker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.

Original languageEnglish (US)
Title of host publicationProceedings - 20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08
Pages465-469
Number of pages5
DOIs
StatePublished - Dec 22 2008
Event20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08 - Dayton, OH, United States
Duration: Nov 3 2008Nov 5 2008

Publication series

NameProceedings - International Conference on Tools with Artificial Intelligence, ICTAI
Volume2
ISSN (Print)1082-3409

Other

Other20th IEEE International Conference on Tools with Artificial Intelligence, ICTAI'08
CountryUnited States
CityDayton, OH
Period11/3/0811/5/08

All Science Journal Classification (ASJC) codes

  • Software
  • Artificial Intelligence
  • Computer Science Applications

Keywords

  • Constraints
  • FPGA
  • Placement
  • Routing
  • Self-organizing feature map

Fingerprint Dive into the research topics of 'Constraint-based placement and routing for FPGAs using self-organizing maps'. Together they form a unique fingerprint.

Cite this