Delay Test Generation: A Hardware Perspective

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Abstract

An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.

Original languageEnglish (US)
Pages (from-to)245-254
Number of pages10
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume10
Issue number3
DOIs
StatePublished - Jan 1 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Keywords

  • Cellular automata
  • Delay test
  • Linear feedback shift register
  • Pseudo-random test
  • Shift dependency
  • Skewed-load delay test
  • Transition test

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