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Delay Test Generation: A Hardware Perspective
Jacob Savir
Electrical and Computer Engineering
Research output
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Contribution to journal
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Review article
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peer-review
6
Scopus citations
Overview
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Dive into the research topics of 'Delay Test Generation: A Hardware Perspective'. Together they form a unique fingerprint.
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Keyphrases
Test Case Generation
100%
Delay Test
100%
Built-in-self-test (BiST)
66%
Test Vector
66%
On chip
33%
Cost Performance
33%
Time Constraints
33%
Delay Faults
33%
Performance Flexibility
33%
Vector Signal Generator
33%
Scan Design
33%
Engineering
Built-in Self Test
100%
Tasks
50%
Cost Performance
50%