Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell

Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a novel ternary Static Random Access Memory (T-SRAM) cell. To validate the functionality of the proposed T-SRAM, carbon nanotube field-effect transistors are selected as a proof-of-concept, whereas either post-CMOS or CMOS technologies can replace it. Our T-SRAM intrinsically eliminates the need to store the intermediate ternary state's voltage level, thus significantly reducing leakage power and increasing robustness. Extensive SPICE simulation and comparison results show that the proposed T-SRAM can be a promising alternative for CMOS SRAMs deploying in low-power edge AI. Further, the analysis verifies that the proposed design is more robust than previous implementations.

Original languageEnglish (US)
Title of host publicationMWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665402798
DOIs
StatePublished - 2022
Event65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022 - Fukuoka, Japan
Duration: Aug 7 2022Aug 10 2022

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2022-August
ISSN (Print)1548-3746

Conference

Conference65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022
Country/TerritoryJapan
CityFukuoka
Period8/7/228/10/22

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Keywords

  • CNFET
  • Multi-Valued Logic
  • Ternary SRAM

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