Design for testability to combat delay faults

Research output: Contribution to conferencePaperpeer-review


To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.

Original languageEnglish (US)
Number of pages5
StatePublished - 1999
EventInternational Conference on Computer Design (ICCD'99) - Austin, TX, USA
Duration: Oct 10 1999Oct 13 1999


ConferenceInternational Conference on Computer Design (ICCD'99)
CityAustin, TX, USA

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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