Abstract
To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.
| Original language | English (US) |
|---|---|
| Pages | 407-411 |
| Number of pages | 5 |
| State | Published - 1999 |
| Event | International Conference on Computer Design (ICCD'99) - Austin, TX, USA Duration: Oct 10 1999 → Oct 13 1999 |
Conference
| Conference | International Conference on Computer Design (ICCD'99) |
|---|---|
| City | Austin, TX, USA |
| Period | 10/10/99 → 10/13/99 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering