Abstract
Recently, jitter is becoming an important performance criterion in switch scheduling to accommodate many emerging real-time applications. Formerly proposed low-jitter scheduling algorithms decompose traffic demands into a weighted sum of permutation matrices and then schedule these decomposed permutation matrices. However, a port pair's appearance in these decomposed matrices may exceed their actual traffic demand. Such extra allocation may result in high jitter for a port pair. In order to smoothly schedule each port pair, we propose a novel scheduling algorithm termed as Dichotomy Slot Allocation (DSA). To achieve low jitter and small cell loss, DSA allocates slots to port pairs based on a designed Dichotomy Order. Both analysis and simulation results demonstrate that DSA achieves relatively lower jitter as compared to the state of the art.
Original language | English (US) |
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Title of host publication | 2007 IEEE Workshop on High Performance Switching and Routing, HPSR |
Pages | 88-93 |
Number of pages | 6 |
DOIs | |
State | Published - Dec 1 2007 |
Event | 2007 IEEE Workshop on High Performance Switching and Routing, HPSR - Brooklyn, NY, United States Duration: May 30 2007 → Jun 1 2007 |
Other
Other | 2007 IEEE Workshop on High Performance Switching and Routing, HPSR |
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Country | United States |
City | Brooklyn, NY |
Period | 5/30/07 → 6/1/07 |
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications