TY - GEN
T1 - Dichotomy slot allocation
T2 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
AU - Zhang, Jingjing
AU - Jin, Yaohui
AU - Ansari, Nirwan
AU - Hu, Weisheng
PY - 2007
Y1 - 2007
N2 - Recently, jitter is becoming an important performance criterion in switch scheduling to accommodate many emerging real-time applications. Formerly proposed low-jitter scheduling algorithms decompose traffic demands into a weighted sum of permutation matrices and then schedule these decomposed permutation matrices. However, a port pair's appearance in these decomposed matrices may exceed their actual traffic demand. Such extra allocation may result in high jitter for a port pair. In order to smoothly schedule each port pair, we propose a novel scheduling algorithm termed as Dichotomy Slot Allocation (DSA). To achieve low jitter and small cell loss, DSA allocates slots to port pairs based on a designed Dichotomy Order. Both analysis and simulation results demonstrate that DSA achieves relatively lower jitter as compared to the state of the art.
AB - Recently, jitter is becoming an important performance criterion in switch scheduling to accommodate many emerging real-time applications. Formerly proposed low-jitter scheduling algorithms decompose traffic demands into a weighted sum of permutation matrices and then schedule these decomposed permutation matrices. However, a port pair's appearance in these decomposed matrices may exceed their actual traffic demand. Such extra allocation may result in high jitter for a port pair. In order to smoothly schedule each port pair, we propose a novel scheduling algorithm termed as Dichotomy Slot Allocation (DSA). To achieve low jitter and small cell loss, DSA allocates slots to port pairs based on a designed Dichotomy Order. Both analysis and simulation results demonstrate that DSA achieves relatively lower jitter as compared to the state of the art.
KW - Dichotomy slot allocation
KW - Input-queued switch
KW - Jitter
UR - http://www.scopus.com/inward/record.url?scp=47649092534&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47649092534&partnerID=8YFLogxK
U2 - 10.1109/HPSR.2007.4281268
DO - 10.1109/HPSR.2007.4281268
M3 - Conference contribution
AN - SCOPUS:47649092534
SN - 1424412064
SN - 9781424412068
T3 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
SP - 88
EP - 93
BT - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Y2 - 30 May 2007 through 1 June 2007
ER -