Distributed BIST architecture to combat delay faults

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To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes three versions of a new design of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Adoption of this new DFT methodology brings us closer to the ideal target of one test-per-clock as opposed to one test-per-scan. Operation, cost, and other attributes are studied in detail. Results of adopting one of these SRLs are reported on ten pilot chips.

Original languageEnglish (US)
Pages (from-to)369-380
Number of pages12
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number4
StatePublished - Aug 2000

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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