Abstract
A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudorandom patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to 'go after' the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.
| Original language | English (US) |
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| Pages | 225-232 |
| Number of pages | 8 |
| State | Published - 1998 |
| Event | Proceedings of the 1998 16th IEEE VLSI Test Symposium - Monterey, CA, USA Duration: Apr 26 1998 → Apr 30 1998 |
Other
| Other | Proceedings of the 1998 16th IEEE VLSI Test Symposium |
|---|---|
| City | Monterey, CA, USA |
| Period | 4/26/98 → 4/30/98 |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering