DOUBLE-PARITY SIGNATURE ANALYSIS FOR LSSD NETWORKS.

J. Savir, W. H. McAnney

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A double-parity self-testing structure for level-sensitive scan design (LSSD) networks is proposed. A vertical parity is taken across all shift register latches on each test, and a longitudinal parity is taken for each latch across all tests. The test application rate is high since each individual clock cycle is a new test. The aliasing probability of the parity check itself is shown to be 2** minus **(**N** plus **K**), where N is the number of applied tests and K is the number of shift register latches. Since the vertical parities (and at the end of the test the longitudinal parities) are compressed in a multiple-input signature register (MISR), the overall aliasing probability is near that of the MISR alone.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherIEEE
Pages510-516
Number of pages7
ISBN (Print)081860798X
StatePublished - Dec 1 1987
Externally publishedYes
EventDig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf - Washington, DC, USA
Duration: Sep 1 1987Sep 3 1987

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

Other

OtherDig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf
CityWashington, DC, USA
Period9/1/879/3/87

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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