A double-parity self-testing structure for level-sensitive scan design (LSSD) networks is proposed. A vertical parity is taken across all shift register latches on each test, and a longitudinal parity is taken for each latch across all tests. The test application rate is high since each individual clock cycle is a new test. The aliasing probability of the parity check itself is shown to be 2** minus **(**N** plus **K**), where N is the number of applied tests and K is the number of shift register latches. Since the vertical parities (and at the end of the test the longitudinal parities) are compressed in a multiple-input signature register (MISR), the overall aliasing probability is near that of the MISR alone.