Effect of BIST pretest on IC defect level

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

Research output: Contribution to journalArticlepeer-review

Abstract

In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to ensure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to get rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when it may be worthwhile to perform it.

Original languageEnglish (US)
Pages (from-to)2626-2636
Number of pages11
JournalIEICE Transactions on Information and Systems
VolumeE89-D
Issue number10
DOIs
StatePublished - Oct 2006

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Keywords

  • BIST
  • Defect level
  • Fault coverage

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