Effect of dry etching and subsequent annealing of Si/SiGe/Si heterostructure

Exposure to dry etching can deleteriously affect strained SiGe films by initiation of misfit strain discontinuity in the film as well as at the interface. In this paper annealing behavior of defects generated as a consequence of dry etching of Si/SiGe/Si heterostructure metal-oxide-semiconductor capacitors have been reported. Some samples were wet etched for comparison. Samples were annealed at four different temperatures after being etched, namely, 650, 700, 750, and 800 °C. Results of the investigations using deep-level transient spectroscopy reveal defect levels at 0.62, 0.57, 0.56, and 0.44 eV for the dry-etched samples and at 0.31, 0.43, 0.56, and 0.44 eV for the wet-etched samples annealed at the aforetold temperatures. The results could be explained on the basis of appearance of point defects condensing into dislocation loops which eventually shrink and disappear as the annealing temperature is increased. The estimated size of the dislocation loops agrees quite well with the experimentally measured values obtained for identically processed samples.